1. Field of the Invention
The present invention relates to a digital AV signal processing apparatus. More particularly, the present invention relates to a digital AV signal processing apparatus capable of controlling a rate of digital-to-analog (hereinafter referred to as D/A) conversion of digital data stored in a buffer.
2. Description of the Related Art
Recently, as computer networks have become widespread, digital audio and video (hereinafter referred to as AV) signals representing AV content are increasingly distributed via computer networks, and the digital AV signals are received by receiver apparatuses while the signals are reproduced (by D/A conversion). Such a form of audience of AV content is becoming popular.
In computer networks, a data transmission rate may fluctuate, causing short-cycle fluctuations (e.g., jitter) in transmitted data. Further, clocks are not synchronized with each other between transmitter apparatuses (e.g., a server and a personal computer) and receiver apparatuses (e.g., a digital AV signal processing apparatus), so that differences in clock between transmitter apparatuses and receiver apparatuses are present.
When typical data to be processed by computers are transmitted, such a jitter or a clock difference does not cause a problem. However, when a digital AV signal is transmitted, a jitter or a clock difference does cause problems. A jitter or a clock difference leads to uncomfortable disruptions in audio or video signals (e.g., sound skip).
Therefore, a D/A conversion rate of digital data stored in a buffer needs to be controlled in order to eliminate uncomfortable disruptions in audio or video signals. To this end, techniques for controlling the D/A conversion rate of digital data stored in a buffer have been developed.
FIG. 12 is a diagram showing a configuration of a conventional digital AV signal processing apparatus 300. The digital AV signal processing apparatus 300 includes a buffer 31, a D/A converter 32, a voltage-controlled oscillator (hereinafter referred to as “VCO”) 33, and a voltage-controlled oscillator controller (hereinafter referred to as “VCO controller”) 34.
The buffer 31 stores digital data which has been input via a transmission system (e.g., a computer network) into the digital AV signal processing apparatus 300, and outputs the digital data as output digital data. The D/A converter 32 converts the output digital data to analog data. A conversion rate of the D/A converter 32 is determined by a clock signal generated by the VCO 33.
When the conversion rate of the D/A converter 32 is greater than an input rate of digital data input to the buffer 31, a data amount of the buffer 31 decreases. When the conversion rate of the D/A converter 32 is smaller than the input rate of digital data input to the buffer 31, the data amount of the buffer 31 increases.
The VCO controller 34 detects the data amount of the buffer 31, and controls the frequency of a clock signal generated by the VCO 33 in such a manner as to cause the conversion rate of the D/A converter 32 to be an appropriate value.
The VCO 33 receives output data DA3 output from the VCO controller 34. The greater the value of the output data DA3 output from the VCO controller 34, the greater the frequency of a clock signal which is controlled by the VCO 33. The smaller the value of the output data DA3 output from the adder 36, the smaller the frequency of a clock signal which is controlled by the VCO 33.
The VCO controller 34 includes a comparator 35, an adder 36, a reference data amount memory 37, and a reference voltage memory 38.
The reference data amount memory 37 stores the amount BHLF of data corresponding to a half of the total capacity of the buffer 31. The reference voltage memory 38 outputs output data DA2 which is used to generate a reference clock frequency. The adder 36 adds the value of output data DA1 with the value of the output data DA2 to output output data DA3.
FIG. 13 is a graph showing an operating characteristic of the comparator 35. The horizontal axis represents the amount BDAT of data in the buffer 31, while the vertical axis represents the output data DA1 output from the comparator 35. BMAX represents the amount of data corresponding to the total capacity of the buffer 31, while BHLF represents the amount of data corresponding to a half of the total capacity of the buffer 31.
As the data amount BDAT increases, the value of the output data DA1 output from the comparator 35 increases. As the value of the output data DA1 increases, the value of the output data DA3 increases. In this case, the frequency of a clock signal generated by the VCO 33 is raised so as to suppress the increase in the data amount BDAT. Conversely, as the data amount BDAT decreases, the value of the output data DA1 output from the comparator 35 decreases. As the value of the output data DA1 decreases, the value of the output data DA3 decreases. In this case, the frequency of a clock signal generated by the VCO 33 is reduced so as to suppress the decrease in the data amount BDAT.
With the above-described operations, the D/A conversion rate of digital data stored in a buffer is controlled.
FIG. 14 is a graph showing a change with time in an input rate of digital data input to the digital AV signal processing apparatus 300. The horizontal axis represents time. The vertical axis represents the input rate of digital data. Short-cycle fluctuations (jitter) in the input rate occur during time periods t1 to t2, t4 to t5, and t7 to t8. During time period t3 to t6, a long-cycle fluctuation occurs due to the unstable clock frequency of a server or a personal computer.
FIG. 15 is a graph showing the data amount of the buffer 31 in the case where digital data is input to the digital AV signal processing apparatus 300 at the input rate shown in FIG. 14. The horizontal axis represents time, while the vertical axis represents the data amount BDAT of the buffer 31. Times t1, t2, t3, t4, t5, t6, t7 and t8 correspond to times t1, t2, t3, t4, t5, t6, t7 and t8 of FIG. 14.
FIG. 16 is a graph showing a frequency of a reproduced clock signal generated by the VCO 33 in the case where digital data is input to the digital AV signal processing apparatus 300 at the input rate shown in FIG. 14. The horizontal axis represents time, while the vertical axis represents a frequency of a reproduced clock signal generated by the VCO 33. Times t1, t2, t3, t4, t5, t6, t7 and t8 respectively correspond to times t1, t2, t3, t4, t5, t6, t7 and t8 of FIG. 14.
Short-cycle fluctuations in the input rate shown in FIG. 14 (see times t1 to t2, t4 to t5, and t7 to t8 in FIG. 14), do not have much influence on the frequency of a reproduced clock signal. In other words, fluctuations (pitch fluctuations) in the frequency of a reproduced clock signal shown in FIG. 16 are suppressed (see times t1 to t2, t4 to t5, and t7 to t8 in FIG. 16), whereby the quality of reproduced sound is improved.
In the conventional digital AV signal processing apparatus 300, however, the frequency of a clock signal is controlled based on a deviation in the data amount of digital data stored in the buffer 31 from a predetermined value (e.g., BHLF, i.e., half the capacity of the buffer 31), whereby even when the data amount BDAT of the digital data stored in the buffer 31 remains constant while being deviated from the predetermined value (time t3 to t6 in FIG. 15), the frequency of a clock signal also remains constant (time t3 to t6 in FIG. 16). Therefore, when the input rate of digital data has long-cycle fluctuations, the data amount of digital data stored in the buffer 31 may remain deviated from the predetermined value. In this situation, overflow or underflow is likely to occur in the buffer.